`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    12:13:13 10/24/2012 
// Design Name: 
// Module Name:    MEM_CTR 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module MEM_CTR #(parameter LOG_DEPTH=8, DEPTH=256, WIDTH=16, OFFSET=0)
(
	
	 input clk,
	 input rst,
	 input [WIDTH-1:0] d_to_wr_r,
	 input [WIDTH-1:0] d_to_wr_i,
	 input [WIDTH-1:0] d_to_rd_r,
	 input [WIDTH-1:0] d_to_rd_i,
	 output reg wr_en,
	 output reg rd_en,
    output[WIDTH-1:0] d_wr_r,
    output[WIDTH-1:0] d_wr_i,
	 output[WIDTH-1:0] d_rd_r,
    output[WIDTH-1:0] d_rd_i,
	 output reg[LOG_DEPTH-1:0] addr_wr,
	 output reg[LOG_DEPTH-1:0] addr_rd
	 
    );
	

	reg[LOG_DEPTH-1:0] count;
	
	assign d_wr_r = d_to_wr_r;
	assign d_wr_i = d_to_wr_i;
	assign d_rd_r = d_to_rd_r;
	assign d_rd_i = d_to_rd_i;
	
	
	always@(posedge clk or negedge rst)
	if(!rst)
		count <= 0;
	else if(count == DEPTH-1)
		count <= 0;
	else
		count <= count + 1;
		
	
	always@(posedge clk or negedge rst)
	if(!rst)
		addr_rd <= 0;
	else
		addr_rd <= addr_wr + count;
		
	
	always@(posedge clk or negedge rst)
	if(!rst)
		addr_wr <= 0;
	else if(count == DEPTH-1)
		addr_wr <= addr_wr + 1;
	else
		addr_wr <= addr_wr;
	
	
	always@(posedge clk or negedge rst)
	if(!rst)
	begin
		wr_en <= 1'b0;
		rd_en <= 1'b0;
	end
	else
	begin
		wr_en <= 1'b1;
		rd_en <= 1'b1;
	end
	
	
endmodule
